1. Field of the Invention
The present invention relates to a method of manufacturing a memory device, and more particularly to a method of manufacturing a bottom electrode of a capacitor of a dynamic random access memory (DRAM).
2. Description of Related Art
Capacitors in the dynamic random access memory (DRAM) are used to store data. The data of each of the memory cells is determined by the charges stored in the corresponding capacitor. The structure of capacitor of DRAM is normally grouped into two major kinds namely, the stack capacitor and the deep trench capacitor. Regardless of the stack capacitor or the deep trench capacitor, the manufacturing technique confronts more and more difficulties under the demands of the small dimension of the semiconductor device.
The crown type capacitors are the stack capacitors widely used in the industry. Generally, the method for manufacturing the crown type capacitor includes forming openings in the silicon oxide template layer, and then depositing conformal conductive layer in the openings and on the silicon oxide template layer. Further, a portion of the conductive layer is removed to isolate different capacitors. Finally, the silicon oxide template layer is removed to form a bottom electrode of the crown type capacitor.
However, with the increasing of the integration of the DRAM, the memory dimension and the area of the capacitor of the DRAM is decreased. Thus, the dimensions of the openings in the silicon oxide template layer for forming the bottom electrode of the crown type capacitor are decreased and the aspect ratio of each of the openings is increased. Since it is not easy to etch the silicon oxide, the lateral etching occurs at the sidewall of the top of each of the openings while the openings are formed. With the increasing of the aspect ratio, the time for performing the etching process is increased and the lateral etching at the sidewall of the top of each opening is much more serious. When the lateral etching at the sidewall of the top of the opening in the silicon oxide template layer is too serious, the adjacent openings communicate to each other at the location on the sidewall where the lateral etching occurs. Hence, the short occurs between the later formed adjacent bottom electrodes corresponding to the adjacent openings. Therefore, it is difficult to decrease the distance between the adjacent openings. Thus, it is hard to increase the lateral area occupied by each of the capacitors or it is hard to increase the integration of the DRAM.